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A model useful for extrapolating yield as a function of chip complexity was recently proposed based on an exercise in mathematical rationalization and some empirical wafer mapping data of discrete IC devices. Recent work using a unique functional diagnostic design will be described which substantially verifies the mode and calibrates it for a customizable, two-layer interconnect, 32-gate DTL array. A simple economic formula will then be used to investigate cost-complexity optimization as a function of wafer and package technology variables. It is concluded that LSI makes sense with optimum single chip gate complexity beginning somewhere between 32 to 64 in 1968 and evolving with time. Multi-LSI-chip system functions probably make even more sense.