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A 3.3 V bandpass ΣΔ modulator for IF sampling at 10.7MHz to be used in radio application has been developed. The modulator presents a 6th-order single-loop architecture and features a 78dB DR with a 200kHz signal bandwidth (FM signal), while for a 9kHz signal bandwidth (AM signal) the DR raises to 93dB. The modulator has been implemented in a standard 0.35µm CMOS technology using SC technique and consumes 80mW from a single 3.3V supply.
Date of Conference: 21-23 Sept. 1999