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Synchronization with multiprocessor caches

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2 Author(s)
J. Lee ; Sch. of Inf. & Comput. Sci., Georgia Inst. of Technol., Atlanta, GA, USA ; U. Ramachandran

A new lock-based cache scheme which incorporates synchronization into the cache coherency mechanism is presented. With this scheme high-level synchronization primitives, as well as low-level ones, can be implemented without excessive overhead. Cost functions for well-known synchronization methods are derived for invalidation schemes, write update schemes, and the authors' lock-based scheme. To predict the performance implications of the new scheme accurately, a new simulation model embodying a widely accepted paradigm of parallel programming is developed. It is shown that that authors' lock-based protocol outperforms existing cache protocols

Published in:

Computer Architecture, 1990. Proceedings., 17th Annual International Symposium on

Date of Conference:

28-31 May 1990