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A Systolic Design-Rule Checker

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2 Author(s)
Kane, R. ; Daisy Systems, San Jose, CA, USA ; Sahni, S.

We develop a systolic design-rule checker (SDRC) for rectilinear geometries. This SDRC reports all width and spacing violations. It is expected to result in a significant speed up of the design-rule check phase of chip design.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:6 ,  Issue: 1 )