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A RISC VLIW processor implements dynamic instruction set extension integrating a pipelined, run-time reconfigurable datapath. A 0.18 /spl mu/m 6M CMOS chip prototype achieves energy consumption reduction up to 90% and time reduction of 13/spl times/ on a signal processing algorithm benchmark. The IC contains 12M transistors and dissipates 120 mW at 80 MHz from a 1.8 V supply.
Date of Conference: 13-13 Feb. 2003