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It has recently been shown that accumulators can be used efficiently for test pattern generation as well as for test response compaction. In this paper we present a BIST scheme for accumulators where the accumulator is simultaneously used as a test pattern generator and a response compactor during its own testing. We also show that the proposed BIST scheme is especially suitable for accumulator, adder and multiplier-accumulator RNS channels leading to minimal hardware overhead and short test sequences.
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on (Volume:5 )
Date of Conference: 25-28 May 2003