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Optimal circuit clustering for delay minimization under a more general delay model

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2 Author(s)
Sze, C.N. ; Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA ; Ting-Chi Wang

This paper considers the area-constrained clustering of combinational circuits for delay minimization under a more general delay model, which practically takes variable interconnect delay into account. Our delay model is particularly applicable when allowing the back-annotation of actual delay information to drive the clustering process. We present a vertex grouping technique and integrate it with the algorithm (Rajaraman and Wong, 1995) such that our algorithm can be proved to solve the problem optimally in polynomial time.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:22 ,  Issue: 5 )

Date of Publication:

May 2003

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