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Simultaneous switching noise in on-chip CMOS power distribution networks

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2 Author(s)
Tang, T.K. ; Broadcom Corp., San Jose, CA, USA ; Friedman, E.G.

Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:10 ,  Issue: 4 )