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A new high-voltage analog-compatible I/sup 2/L process

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5 Author(s)

A new technique for realizing high-performance I/SUP 2/L circuits simultaneously with high-voltage analog circuits is described. The method is flexible and may be used with any standard linear bipolar process. Only one additional noncritical masking step and one phosphorus implant are required to form the I/SUP 2/L n-wells. Experimental results are presented which show I/SUP 2/L betas of greater than eight per collector with the I/SUP 2/L BV/SUB CEO/ exceeding 3 V. The measured minimum average propagation delay is 40 ns using a 14 /spl mu/m thick, 5 /spl Omega/.cm epitaxial layer, while the analog BV/SUB CEO/ exceeds 50 V.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:13 ,  Issue: 4 )

Date of Publication:

Aug. 1978

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