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This paper describes a Self-Timed MOS Current-Mode Logic (ST-MCML) for digital applications. The architecture and operation of ST-MCML is explained and analyzed. 4-bit ripple and 16-bit carry look ahead adders are implemented using the ST-MCML technique in a 0.18-μm, 1.8-V, 1-GHz CMOS process. ST-MCML is compared to conventional MCML, static CMOS and domino logic in terms of power, delay, Power-Delay-Product (PDP) and Energy-Delay-Product (EDP). ST-MCML achieves low-power values as well as minimum PDP and EDP values.