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A capacitorless double-gate DRAM cell

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3 Author(s)
C. Hu ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Tsu-Jae King ; Chenming Hu

A capacitorless double-gate DRAM (DG-DRAM) cell is proposed in this study. Its dual gates and thin body reduce off state leakage and. disturb problems. Dopant fluctuations, which can be particularly important in high-density arrays, are avoided by using a thin, lightly doped body. The cell's large body coefficient ((dV/sub T/)/(dV/sub BD/) transforms small gains of body potential into increased drain current. MEDICI simulations for 85/spl deg/C show that a DG-DRAM cell may sustain a measurable change in drain current several hundred milliseconds after programming. These characteristics suggest that a thin body, double-gate cell is an interesting candidate for high density DRAM technologies.

Published in:

IEEE Electron Device Letters  (Volume:23 ,  Issue: 6 )