A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA
Xiaohua Fan
Heng Zhang
Sanchez-Sinencio, E.
Texas A&M Univ., Austin;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: March 2008
Volume: 43,
Issue: 3
On page(s): 588-599
Location: Lille, France,
ISSN: 0018-9200
INSPEC Accession Number: 9818881
Digital Object Identifier: 10.1109/JSSC.2007.916584
Current Version Published: 2008-02-25
Abstract
A typical common source cascode low-noise amplifier (CS-LNA) can be treated as a CS-CG two stage amplifier. In the published literature, an inductor is added at the drain of the main transistor to reduce the noise contribution of the cascode transistors. In this work, an inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically combined to reduce the noise and the nonlinearity influences of the cascode transistors in a differential cascode CS-LNA. It uses a smaller noise reduction inductor compared with the conventional inductor based technique. It can reduce the noise, improve the linearity and also increase the voltage gain of the LNA. The proposed technique is theoretically formulated. Furthermore, as a proof of concept, a 2.2 GHz inductively degenerated CS-LNA was fabricated using TSMC 0.35 mum CMOS technology. The resulting LNA achieves 1.92 dB noise figure, 8.4 dB power gain, better than 13 dB S11, more than 30 dB isolation (S12), and -2.55 dBm IIP3, with the core fully differential LNA consuming 9 mA from a 1.8 V power supply.
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