A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications
Geum-Young Tak
Seok-Bong Hyun
Tae Young Kang
Byoung Gun Choi
Seong Su Park
Basic Res. Lab., Electron. & Telecommun. Res. Inst., Daejeon, South Korea;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Aug. 2005
Volume: 40,
Issue: 8
On page(s): 1671- 1679
ISSN: 0018-9200
INSPEC Accession Number: 8507629
Digital Object Identifier: 10.1109/JSSC.2005.852421
Current Version Published: 2005-07-25
Abstract
A CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336 and 8.976 GHz in steps of 528 MHz and settles in approximately 150 ns is presented. The proposed PLL can be employed as a building block for a frequency synthesizer which generates a seven-band hopping carrier for multiband orthogonal frequency division multiplexing (MB-OFDM) ultrawideband (UWB) radio. To achieve fast loop settling, integer-N architecture that operates with 528-MHz reference frequency is implemented and a wideband active-loop filter is integrated. An improved phase-frequency detector (PFD) is proposed for faster loop settling. To reduce reference sidebands, a feedback circuit using replica bias is implemented in the charge pump. I/Q carriers are generated by two cross-coupled LC VCOs. The output current of the charge pump is controlled to compensate for the VCO gain nonlinearity and a programmable frequency divider (12≤N≤17) that reliably operates at 9 GHz is designed. Fabricated in 0.18-μm CMOS technology, the PLL consumes 32 mA from a 1.8-V supply and achieves phase noise of -109.6dBc/Hz at 1-MHz offset and spurs of -52 dBc.
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