A compact model of MOSFET mismatch for circuit design
Galup-Montoro, C.
Schneider, M.C.
Klimach, H.
Arnaud, A.
Electr. Eng. Dept., Fed. Univ. of Santa Catarina, Florianopolis, Brazil;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Aug. 2005
Volume: 40,
Issue: 8
On page(s): 1649- 1657
ISSN: 0018-9200
INSPEC Accession Number: 8507626
Digital Object Identifier: 10.1109/JSSC.2005.852045
Current Version Published: 2005-07-25
Abstract
This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 μm technology confirm the accuracy of our mismatch model under various bias conditions.
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
