A 21ns 32K×8 CMOS SRAM with a selectively pumped P-well array
Wang, K.
Bader, M.
Voss, P.
Soorholtz, V.
Mauntel, R.
Mendez, H.
Kung, R.
Motorola Memory Products Division, Austin, TX;
Abstract
A selectivity pumped P-well array used in a 32K×8 CMOS SRAM with a divided-word line block architecture to achieve a 21ns access time, will be described. The chip (6.83×8.97mm) was processed in a 1.2μm double-level metal, twin-well CMOS technology. Active power is 330mW at 22MHz.
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