Integration difficulties and limitations in sub-0.25 μm CMOS andCMOS-based technologies
Deferm, L.
Badenes, G.
Silicon Device & Process Integration Div., IMEC, Leuven;
This paper appears in: Microelectronics, 2000. Proceedings. 2000 22nd International Conference on
Publication Date: 2000
Volume: 2,
On page(s): 399-406 vol.2
Meeting Date: 05/14/2000 - 05/17/2000
Location: Nis, Yugoslavia
ISBN: 0-7803-5235-1
References Cited: 31
INSPEC Accession Number: 6644195
Digital Object Identifier: 10.1109/ICMEL.2000.838721
Current Version Published: 2002-08-06
Abstract
Market demands, which require increased functionality at lower
costs are driving the development of high performance CMOS technologies
with very high integration density. These demands are pushing the
continuous scaling down of technologies and are resulting in a
progressive acceleration of the rate of introduction of new technology
generations. Current research and development activities in CMOS
technology are focused on scaling the 0.25 μm CMOS technology
generation down to 0.18 μm or even 0.13 μm dimensions. While some
of the process modules can be scaled down in a conventional way, in some
cases severe limitations are reached and it is necessary to introduce
major modifications to the process flow. In this paper we will present
an overview of the main considerations to be kept in mind when scaling
down to a 0.18 pm CMOS technology generation
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
