SCALIP - a scalable IP solution for pipelined arrays with limitedfeedback
Moe, M.
Schmit, H.
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA;
This paper appears in: ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Publication Date: 2001
On page(s): 334-338
Meeting Date: 09/12/2001 - 09/15/2001
Location: Arlington, VA, USA
ISBN: 0-7803-6741-3
References Cited: 11
INSPEC Accession Number: 7154584
Digital Object Identifier: 10.1109/ASIC.2001.954723
Current Version Published: 2002-08-07
Abstract
Current IP methodologies are only useful within a limited design
space low power, high performance or low area. A single IP methodology
is needed that can span all of these design spaces with one
specification. SCALIP is a methodology that can quickly and easily
create multiple design points that span a much greater design space thin
any current IP methodology utilizing only behavioral or RTL synthesis.
One limitation of this methodology is that it is only useful for
pipelined arrays with limited feedback
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