Hiding relaxed memory consistency with a compiler
Lee, J.
Padua, D.A.
Dept. of Comput. Sci. & Eng., Michigan State Univ., East Lansing, MI;
This paper appears in: Computers, IEEE Transactions on
Publication Date: Aug 2001
Volume: 50,
Issue: 8
On page(s): 824-833
Meeting Date: 10/15/2000 - 10/19/2000
Location: Philadelphia, PA, USA
ISSN: 0018-9340
References Cited: 41
CODEN: ITCOB4
INSPEC Accession Number: 7039689
Digital Object Identifier: 10.1109/12.947002
Current Version Published: 2002-08-07
Abstract
We present a compiler technique, which is based on Shasha and
Snir's delay set analysis, to hide the underlying relaxed memory
consistency model for an optimizing compiler for explicitly parallel
programs. The compiler presents programmers with a sequentially
consistent view of the underlying machine, irrespective of whether it
follows a sequentially consistent model or a relaxed model. To hide the
underlying relaxed memory consistency model and to guarantee sequential
consistency, our algorithm inserts fence instructions by identifying
memory-barrier nodes. We reduce the number of fence instructions by
exploiting the ordering constraints of the underlying memory consistency
model and the property of fence and synchronization operations. We
introduce dominators with respect to a node in a control flow graph to
identify memory-barrier nodes and show that minimizing the number of
memory-barrier nodes is NP-hard
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