Activity-driven clock design
Farrahi, A.H.
Chunhong Chen
Srivastava, A.
Tellez, G.
Sarrafzadeh, M.
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY;
Abstract
In this paper, we investigate reducing the power consumption of a
synchronous digital system by minimizing the total power consumed by the
clock signals. We construct activity-driven clock trees wherein sections
of the clock tree are turned off by gating the clock signals. Since
gating the clock signal implies that additional control signals and
gates are needed, there exists a tradeoff between the amount of clock
tree gating and the total power consumption of the clock tree. We
exploit similarities in the switching activity of the clocked modules to
reduce the number of clock gates. Assuming a given switching activity of
the modules, we propose three novel activity-driven problems: a clock
tree construction problem, a clock gate insertion problem, and a
zero-skew clock gate insertion problem. The objective of these problems
is to minimize the system's power consumption by constructing an
activity-driven clock tree. We propose an approximation algorithm based
on recursive matching to solve the clock tree construction problem. We
also propose an exact algorithm employing the dynamic programming
paradigm to solve the gate insertion problems. Finally, we present
experimental results that verify the effectiveness of our approach. This
paper is a step in understanding how high-level decisions (e.g.,
behavioral design) can affect a low-level design (e.g., clock design)
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