1/f noise in CMOS transistors for analog applications
Nemirovsky, Y.
Brouk, I.
Jakobson, C.G.
Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa;
This paper appears in: Electron Devices, IEEE Transactions on
Publication Date: May 2001
Volume: 48,
Issue: 5
On page(s): 921-927
ISSN: 0018-9383
References Cited: 25
CODEN: IETDAI
INSPEC Accession Number: 6921684
Digital Object Identifier: 10.1109/16.918240
Current Version Published: 2002-08-07
Abstract
Noise measurements of the 1/f noise in PMOS and NMOS transistors
for analog applications are reported under wide bias conditions ranging
from subthreshold to saturation. Two “low noise” CMOS
processes of 2 μm and 0.5 μm technologies are compared and it is
found that the more advanced process, with 0.5 μm technology,
exhibits significantly reduced 1/f noise, due to optimized processing.
The input referred noise and the power spectral density (PSD) of the
drain current 1/f noise are modeled in saturation as well as in
subthreshold and are compared with the common empirical approaches such
as the SPICE models. The results of this study are useful to the design
and modeling of 1/f noise of CMOS analog circuits
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