Implementation of near Shannon limit error-correcting codes usingreconfigurable hardware
Levine, B.
Reed Taylor, R.
Schmit, H.
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA;
This paper appears in: Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on
Publication Date: 2000
On page(s): 217-226
Meeting Date: 04/17/2000 - 04/19/2000
Location: Napa Valley, CA, USA
ISBN: 0-7695-0871-5
References Cited: 17
INSPEC Accession Number: 6853668
Digital Object Identifier: 10.1109/FPGA.2000.903409
Current Version Published: 2002-08-06
Abstract
Error correcting codes (ECCs) are widely used in digital
communications. New types of ECCs have been proposed which permit
error-free data transmission over noisy channels at rates which approach
the Shannon capacity. For wireless communication, these new codes allow
more data to be carried in the same spectrum, lower transmission power,
and higher data security and compression. One new type of ECC, referred
to as Turbo Codes, has received a lot of attention, but is
computationally expensive to decode and difficult to realize in
hardware. Low density parity check codes (LDPCs), another ECC, also
provide near Shannon limit error correction ability. However, LDPCs use
a decoding scheme which is much more amenable to hardware
implementation. This paper first presents an overview of these coding
schemes, then discusses the issues involved in building an LDPC decoder
using reconfigurable hardware. It presents a hypothetical LDPC
implementation using a commercial FPGA, which will give an idea of
future research issues and performance gains
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