PipeRench implementation of the Instruction Path Coprocessor
Yuan Chou
Pillai, P.
Schmit, H.
Shen, J.P.
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA;
This paper appears in: Microarchitecture, 2000. MICRO-33. Proceedings. 33rd Annual IEEE/ACM International Symposium on
Publication Date: 2000
On page(s): 147-158
Meeting Date: 12/10/2000 - 12/13/2000
Location: Monterey, CA, USA
ISBN: 0-7695-0924-X
References Cited: 26
INSPEC Accession Number: 6839529
Digital Object Identifier: 10.1109/MICRO.2000.898066
Current Version Published: 2002-08-06
Abstract
The paper demonstrates how an Instruction Path Coprocessor (I-COP)
can be efficiently implemented using the PipeRench reconfigurable
architecture. An I-COP is a programmable on-chip coprocessor that
operates on the core processor's instructions to transform them into a
new format that can be more efficiently executed. The I-COP can be used
to implement many sophisticated hardware code modification techniques.
We show how four specific techniques can be mapped to the PipeRench
pipelined computation model. The experimental results show that a
PipeRench I-COP used to perform trace construction and trace
optimizations for a trace cache fill unit not only achieves good
performance gains but can potentially be implemented in less than 10 mm
2 (assuming 0.18 micron technology) or approximately 3% of
the die area of a current high-end microprocessor. We believe these
results demonstrate the usefulness and feasibility of the I-COP concept
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
