Single chip implementation of the 1.6 kbps speech vocoder
Jia-Ching Wang
Jhing-Fa Wang
Han-Chiang Chen
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan;
This paper appears in: Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Publication Date: 2000
Volume: 5,
On page(s): 597-600 vol.5
Meeting Date: 05/28/2000 - 05/31/2000
Location: Geneva, Switzerland
ISBN: 0-7803-5482-6
References Cited: 4
INSPEC Accession Number: 6777224
Digital Object Identifier: 10.1109/ISCAS.2000.857506
Current Version Published: 2002-08-06
Abstract
In this paper, we propose a low bit rate speech vocoder and its
corresponding VLSI implementation. The vocoder exploits the
interpolation property so that the fine quality in synthesized speech is
obtained even though the bit rate is as low as 1.6 kbps. Two novel
methods including pitch detection and LSP decoding which are suitable
for VLSI implementation are also proposed. The heuristic pitch detection
algorithm avoids the heavy computational load introduced by the
traditional normalized autocorrelation method. The memory storing
triangular function value is no longer needed after adopting the new LSP
decoding process. The chip is designed with area effective feature and
is suitable for stand alone application
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