PipeRench: a reconfigurable architecture and compiler
Goldstein, S.C.
Schmit, H.
Budiu, M.
Cadambi, S.
Moe, M.
Taylor, R.R.
Carnegie Mellon Univ., Pittsburgh, PA;
This paper appears in: Computer
Publication Date: Apr 2000
Volume: 33,
Issue: 4
On page(s): 70-77
ISSN: 0018-9162
References Cited: 7
CODEN: CPTRB4
INSPEC Accession Number: 6578149
Digital Object Identifier: 10.1109/2.839324
Current Version Published: 2002-08-06
Abstract
With the proliferation of highly specialized embedded computer
systems has come a diversification of workloads for computing devices.
General-purpose processors are struggling to efficiently meet these
applications' disparate needs, and custom hardware is rarely feasible.
According to the authors, reconfigurable computing, which combines the
flexibility of general-purpose processors with the efficiency of custom
hardware, can provide the alternative. PipeRench and its associated
compiler comprise the authors' new architecture for reconfigurable
computing. Combined with a traditional digital signal processor,
microcontroller or general-purpose processor, PipeRench can support a
system's various computing needs without requiring custom hardware. The
authors describe the PipeRench architecture and how it solves some of
the pre-existing problems with FPGA architectures, such as logic
granularity, configuration time, forward compatibility, hard constraints
and compilation time
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