Wavefront scheduling: path based data representation and schedulingof subgraphs
Bharadwaj, J.
Menezes, K.
McKinsey, C.
Intel Corp., Santa Clara, CA;
This paper appears in: Microarchitecture, 1999. MICRO-32. Proceedings. 32nd Annual International Symposium on
Publication Date: 1999
On page(s): 262-271
Meeting Date: 11/16/1999 - 11/18/1999
Location: Haifa, Israel
ISBN: 0-7695-0437-X
References Cited: 14
INSPEC Accession Number: 6431214
Digital Object Identifier: 10.1109/MICRO.1999.809464
Current Version Published: 2002-08-06
Abstract
The IA-64 architecture is rich with features that enable
aggressive exploitation of instruction-level parallelism. Features such
as speculation, predication, multiway branches and others provide
compilers with new opportunities for the extraction of parallelism in
programs. Code scheduling is a central component in any compiler for the
IA-64 architecture. This paper describes the implementation of the
global code scheduler (GCS) in Intel's reference compiler for the IA-64
architecture. GCS schedules code over acyclic regions of control flow.
There is a tight coupling between the formation and scheduling of
regions. GCS employs a new path based data dependence representation
that combines control flow and data dependence information to make data
analysis easy and accurate. This paper provides details of this
representation. The scheduler uses a novel instruction scheduling
technique called Wavefront scheduling. The concepts of wavefront
scheduling and deferred compensation are explained to demonstrate the
efficient generation of compensation code while scheduling. This paper
also presents P-ready code motion, an opportunistic instruction level
tail duplication which aims to strike a balance between code expansion
and performance potential. Performance results show greater than 30%
improvement in speedup for wavefront scheduling over basic block
scheduling on the Merced microarchitecture
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