Minimizing the required memory bandwidth in VLSI systemrealizations
Wuytack, S.
Catthoor, F.
De Jong, G.
De Man, H.J.
Inter-Univ. Micro-Electron. Centre, Leuven;
This paper appears in: Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publication Date: Dec 1999
Volume: 7,
Issue: 4
On page(s): 433-441
ISSN: 1063-8210
References Cited: 21
CODEN: IEVSE9
INSPEC Accession Number: 6449301
Digital Object Identifier: 10.1109/92.805750
Current Version Published: 2002-08-06
Abstract
In this paper, we present the problem of storage bandwidth
optimization (SBO) in VLSI system realizations. Our goal is to minimize
the required memory bandwidth within the given cycle budget by adding
ordering constraints to the flow graph. This allows the subsequent
memory allocation and assignment tasks to come up with a cheaper memory
architecture with less memories and memory ports. The importance and the
effect of SBO is shown on realistic examples both in the video and
asynchronous transfer-mode (ATM) domains. We show that it is important
to take into account which data is being accessed in parallel, instead
of only considering the number of simultaneous memory accesses. Our
problem formulation leads to the optimization of a conflict (hyper)
graph. For the target domain of ATM, only flat graphs without loops have
to be treated. For this subproblem, a prototype tool has been
implemented to demonstrate the feasibility of automating this important
system design step
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