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Mixed-swing quadrail for low power dual-rail domino logic
Ramasubramanian, B. Schmit, H. Carley, L.R.
SUN Microsyst., Sunnyvale, CA, USA;

This paper appears in: Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on
Publication Date: 1999
On page(s): 82- 84
ISSN:
ISBN: 1-58113-133-X
INSPEC Accession Number: 6520182
Current Version Published: 2005-05-23

Abstract
This paper describes a new mixed-swing topology for dual-rail domino logic that results in a simultaneous energy and delay reduction. HSPICE simulation results for a 1-bit full adder cell show a 24% delay decrease and a 24% energy reduction for the mixed-swing topology compared to standard dual-rail domino. Energy and delay trends with supply voltage scaling are also presented for the adder cell. An 8-bit by 8-bit multiplier design with mixed-swing dual-rail domino adders is presented. Simulation results show this implementation to be 10% faster with an 18% energy savings.

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