PipeRench: a coprocessor for streaming multimedia acceleration
Goldstein, S.C.
Schmit, H.
Moe, M.
Budiu, M.
Cadambi, S.
Taylor, R.R.
Laufer, R.
Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA;
This paper appears in: Computer Architecture, 1999. Proceedings of the 26th International Symposium on
Publication Date: 1999
On page(s): 28-39
Meeting Date: 05/02/1999 - 05/04/1999
Location: Atlanta, GA, USA
ISBN: 0-7695-0170-2
References Cited: 29
INSPEC Accession Number: 6346049
Digital Object Identifier: 10.1109/ISCA.1999.765937
Current Version Published: 2002-08-06
Abstract
Future computing workloads will emphasize an architecture's
ability to perform relatively simple calculations on massive quantities
of mixed-width data. This paper describes a novel reconfigurable fabric
architecture, PipeRench, optimized to accelerate these types of
computations. PipeRench enables fast, robust compilers, supports forward
compatibility, and virtualizes configurations, thus removing the fixed
size constraint present in other fabrics. For the first time we explore
how the bit-width of processing elements affects performance and show
how the PipeRench architecture has been optimized to balance the needs
of the compiler against the realities of silicon. Finally, we
demonstrate extreme performance speedup on certain computing kernels (up
to 190x versus a modern RISC processor), and analyze how this
acceleration translates to application speedup
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