HARTS: a distributed real-time architecture
Shin, K.G.
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI;
This paper appears in: Computer
Publication Date: May 1991
Volume: 24,
Issue: 5
On page(s): 25-35
ISSN: 0018-9162
References Cited: 12
CODEN: CPTRB4
INSPEC Accession Number: 3938358
Digital Object Identifier: 10.1109/2.76284
Current Version Published: 2002-08-06
Abstract
The design, implementation, and evaluation of a distributed
real-time architecture called HARTS (hexagonal architecture for
real-time systems) are discussed, emphasizing its support of
time-constrained, fault-tolerant communications and I/O (input/output)
requirements. HARTS consists of shared-memory multiprocessor nodes,
interconnected by a wrapped hexagonal mesh. This architecture is
intended to meet three main requirements of real-time computing: high
performance, high reliability, and extensive I/O. The high-level and
low-level architecture is described. The evaluation of HARTS, using
modeling and simulation with actual parameters derived from its
implementation, is reported. Fault-tolerant routing, clock
synchronization and the I/O architecture are examined
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