Characterization and parameterization of a pipeline reconfigurableFPGA
Moe, M.
Schmit, H.
Goldstein, S.C.
Carnegie Mellon Univ., Pittsburgh, PA;
This paper appears in: FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on
Publication Date: 15-17 Apr 1998
On page(s): 294-295
Meeting Date: 04/15/1998 - 04/17/1998
Location: Napa Valley, CA, USA
ISSN: 1082-3409
ISBN: 0-8186-8900-5
References Cited: 5
INSPEC Accession Number: 6035005
Digital Object Identifier: 10.1109/FPGA.1998.707923
Current Version Published: 2002-08-06
Abstract
The article defines a class of architectures for pipeline
reconfigurable FPGAs by parameterizing a generic model. This class of
architecture is sufficiently general to allow exploration of the most
important design trade-offs. The parameters include the word size and
LUT size, the number of global busses and registers associated with each
logic block, and the horizontal interconnect within each stripe. We have
developed an area model for the architecture that allows us to quickly
estimate the area of an instance of the architectural class as a
function of the parameter values. We compare the estimates generated by
this model to one instance of the architecture that we have designed and
fabricated
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