Module packing based on the BSG-structure and IC layoutapplications
Nakatake, S.
Fujiyoshi, K.
Murata, H.
Kajitani, Y.
Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol.;
Abstract
A new method of packing the rectangles is proposed with
applications to integrated circuit (IC) layout design. A special
work-sheet, called the bounded-sliceline grid, is introduced. It
consists of special segments that dissect the plane into rooms to which
binary relations “right-of” and “above” are
associated such that any two rooms are uniquely in either relation. A
packing is obtained through an assignment of the modules into the rooms
followed by a compaction procedure. Changing the assignments by swapping
the contents of two rooms, a simulated annealing strategy is implemented
to search for a good packing. Empirical results show that hundreds of
rectangles are packed with a quite good quality in area efficiency. A
wide adaptability is demonstrated specific to IC layout design. Ideas to
handle a multilayer, nonrectangular chips with L-shaped modules are
suggested
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