A low-power 16-bit multiplier-accumulator using series-regulatedmixed swing techniques
Krishnamurthy, R.K.
Schmit, H.
Carley, L.R.
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA;
This paper appears in: Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Publication Date: 11-14 May 1998
On page(s): 499-502
Meeting Date: 05/11/1998 - 05/14/1998
Location: Santa Clara, CA, USA
ISBN: 0-7803-4292-5
References Cited: 12
INSPEC Accession Number: 6118352
Digital Object Identifier: 10.1109/CICC.1998.695027
Current Version Published: 2002-08-06
Abstract
This paper describes an on-chip series-regulated mixed swing
methodology with sleep-mode control for lowering the power consumption
of high-performance DSP multiplier-accumulator (MAC) circuits. A
16*16+36-bit overlapped bit-pair Booth recoded Wallace tree MAC is
fabricated in a commercial 0.5 μm CMOS process in the proposed
series-regulated methodology and conventional static CMOS. Up to
2.55× reduction in energy/operation is measured over static CMOS,
while offering a simultaneous 1.8× improvement in low-voltage
manufacturability. At the maximum clock frequency of 67 MHz, the
proposed approach consumes a total MAC power of 16.6 mW in active mode
and 152.5 nW in standby mode. Measured peak-peak power/ground bounce is
under 8% of the regulated low-swing voltage. Experimental results from
comparisons in three additional (0.35 μm, 0.25 μm, 0.16 μm)
CMOS and fully-depleted SOI processes are also presented to demonstrate
improved savings over static CMOS with process scaling
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