Layout generation algorithm for CMOS analog IC cells
Tsien Liang
Syrzycki, M.
Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC ;
This paper appears in: Electrical and Computer Engineering, 1998. IEEE Canadian Conference on
Publication Date: 24-28 May 1998
Volume: 2,
On page(s): 653-656 vol.2
Meeting Date: 05/24/1998 - 05/28/1998
Location: Waterloo, Ont., Canada
ISBN: 0-7803-4314-X
References Cited: 5
INSPEC Accession Number: 6127328
Digital Object Identifier: 10.1109/CCECE.1998.685581
Current Version Published: 2002-08-06
Abstract
This paper presents the development of an algorithm for the
placement of transistors in analog IC layout design. The properties and
implementation techniques of the algorithm are introduced along with
sample layouts produced for a test circuit
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