INALSYS: a layout automation system based on analog layout constraints
Youngsoo Kim
Hyunsang Cho
Kwangsub Yoon
Dept. of Electron. Eng., Inha Univ., Inchon, South Korea;
This paper appears in: Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Publication Date: 3-6 Aug. 1997
Volume: 2,
On page(s): 1209- 1212 vol.2
ISBN: 0-7803-3694-1
INSPEC Accession Number: 5945878
Digital Object Identifier: 10.1109/MWSCAS.1997.662297
Current Version Published: 2002-08-06
Abstract
An analog layout system that can handle analog constraints is presented in this paper. In order to process the analog layout constraints, parameterizable module library and the effective floorplanning model that encapsulates well-merging is proposed. Also, global routing algorithm is modified by adopting divide-by-triangle method. This layout system has been tested on several benchmark circuits and displayed comparable results to the conventional layout system in terms of layout quality, expandability and execution time.
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
