Incremental reconfiguration for pipelined applications
Schmit, H.
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA;
This paper appears in: FPGAs for Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on
Publication Date: 16-18 Apr 1997
On page(s): 47-55
Meeting Date: 04/16/1997 - 04/18/1997
Location: Napa Valley, CA, USA
ISBN: 0-8186-8159-4
References Cited: 8
INSPEC Accession Number: 5731374
Digital Object Identifier: 10.1109/FPGA.1997.624604
Current Version Published: 2002-08-06
Abstract
This paper examines the implementation of pipelined applications
using run-time reconfiguration. Throughput and latency of pipelined
applications can be significantly improved when reconfiguration is
performed at the level of individual pipeline stages, as opposed to
configuration of the entire FPGA. If reconfiguration and execution can
be performed simultaneously, the performance of a pipelined application
approaches its theoretical maximum. This paper proposes a new FPGA
configuration mechanism, called striping, that supports pipeline stage
reconfiguration and simultaneous configuration and execution.
Additionally, the use of the pipeline stage as the atomic unit of
reconfiguration introduces a design abstraction that enables the
development families of upwardly-compatible FPGAs and virtual hardware
design
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