Data-driven self-timed RSFQ digital integrated circuit and system
Deng, Z.J.
Yoshikawa, N.
Whiteley, S.R.
Van Duzer, T.
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA;
This paper appears in: Applied Superconductivity, IEEE Transactions on
Publication Date: Jun 1997
Volume: 7,
Issue: 2, Part 3
On page(s): 3634-3637
Meeting Date: 08/25/1996 - 08/30/1996
Location: Pittsburgh, PA, USA
ISSN: 1051-8223
References Cited: 7
CODEN: ITASE9
INSPEC Accession Number: 5702336
Digital Object Identifier: 10.1109/77.622205
Current Version Published: 2002-08-06
Abstract
A novel asynchronous timing scheme, data-driven self-timing (DDST)
is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ)
superconductive integrated circuits. In this asynchronous approach, the
timing signals are generated from the data and no global clock is needed
to drive the RSFQ circuit and system. The essence of the self-timing
scheme is to localize the system timing in order to avoid the overhead
of global clock distribution, and to minimize the timing uncertainty.
The DDST scheme has been applied to the design of a shift register, a
demultiplexor, and a self-timed high speed digital test system. In this
paper, test results of a 4-bit DDST shift register and a high speed
on-chip clock generator will be presented to demonstrate the successful
DDST operation of RSFQ integrated circuits at a rate of 20 Gb/s
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