Will physical scalability sabotage performance gains?
Matzke, D.
Texas Instrum. Inc.;
This paper appears in: Computer
Publication Date: Sep 1997
Volume: 30,
Issue: 9
On page(s): 37-39
ISSN: 0018-9162
References Cited: 5
CODEN: CPTRB4
INSPEC Accession Number: 5699438
Digital Object Identifier: 10.1109/2.612245
Current Version Published: 2002-08-06
Abstract
The most important physical trend facing chip architects is the
fact that on-chip wires are becoming much slower relative to logic as
the on-chip devices shrink. The author points out that it will soon be
impossible to maintain one global clock over the entire chip, and
sending signals across a billion-transistor processor may require as
many as 20 cycles
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