Parallel logic simulation on a workstation cluster
Murakami, T.
Wada, K.
Okano, S.
Tsukuba Univ., Ibaraki;
This paper appears in: Communications, Computers, and Signal Processing, 1995. Proceedings. IEEE Pacific Rim Conference on
Publication Date: 17-19 May 1995
On page(s): 268-271
Meeting Date: 05/17/1995 - 05/19/1995
Location: Victoria, BC, Canada
ISBN: 0-7803-2553-2
References Cited: 8
INSPEC Accession Number: 5112550
Digital Object Identifier: 10.1109/PACRIM.1995.519459
Current Version Published: 2002-08-06
Abstract
A high speed logic simulator is a requisite tool in designing
VLSIs. This paper presents a high performance parallel logic simulator
on a workstation cluster. The conservative method is used for an
algorithm of parallel logic simulator. The null message and the query
computation algorithm are used to solve deadlocks. This paper proposes
an event clumping that can reduce the number of messages effectively.
The simulation has been performed on the workstation cluster for
evaluation. The results of evaluation showed that the proposed method
exhibited the speed of 42 times faster than the conventional null
message algorithm. In the case of the query computation algorithm, the
gain of the event clumping was 4.2 on five processors
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