Abstract
This paper presents techniques for generating addresses for
memories containing multiple arrays. Because these techniques rely on
the inversion or rearrangement of address bits, they are faster and
require less hardware to compute than offset addition. Use of these
techniques can decrease effective access time to arrays and reduce
address generation hardware. The primary drawback is that extra memory
space is occasionally required by these techniques, but this extra
memory space is on average only 4% and no worse than 25.2% of the
utilized memory space. This amount of wasted address space is less than
the amount required by similar techniques
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