Reproducible simulation of multi-threaded workloads for architecture design exploration
Pereira, C.
Patil, H.
Calder, B.
Comput. Sci. & Eng., Univ. of California, La Jolla, CA;
This paper appears in: Workload Characterization, 2008. IISWC 2008. IEEE International Symposium on
Publication Date: 14-16 Sept. 2008
On page(s): 173-182
Location: Seattle, WA,
ISBN: 978-1-4244-2777-2
INSPEC Accession Number: 10283905
Digital Object Identifier: 10.1109/IISWC.2008.4636102
Current Version Published: 2008-09-30
Abstract
As multiprocessors become mainstream, techniques to address efficient simulation of multi-threaded workloads are needed. Multi-threaded simulation presents a new challenge: non-determinism across simulations for different architecture configurations. If the execution paths between two simulation runs of the same benchmark with the same input are too different, the simulation results cannot be used to compare the configurations. In this paper we focus on a simulation technique to efficiently collect simulation checkpoints for multi-threaded workloads, and to compare simulation runs addressing this non-determinism problem. We focus on user-level simulation of multi-threaded workloads for multiprocessor architectures. We present an approach, based on binary instrumentation, to collect checkpoints for simulation. Our checkpoints allow reproducible execution of the samples across different architecture configurations by controlling the sources of nondeterminism during simulation. This results in stalls that would not naturally occur in execution. We propose techniques that allow us to accurately compare performance across architecture configurations in the presence of these stalls.
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