Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits
Little, S.
Sen, A.
Myers, C.
Sch. of Comput., Univ. of Utah, Salt Lake City, UT;
This paper appears in: Microprocessor Test and Verification, 2007. MTV '07. Eighth International Workshop on
Publication Date: 5-6 Dec. 2007
On page(s): 109-115
Location: Austin, TX,
ISSN: 1550-4093
ISBN: 978-0-7695-3241-7
INSPEC Accession Number: 10207389
Digital Object Identifier: 10.1109/MTV.2007.17
Current Version Published: 2008-09-05
Abstract
Abstract models of analog/mixed-signal (AMS) circuits can be used for formal verification and system-level simulation. The difficulty of creating these models precludes their widespread use. This paper presents an automated method to generate abstract models appropriate for system-level simulation and formal verification. This method uses simulation traces and thresholds on the design variables to generate a piecewise-linear representation of the system. This piecewise-linear representation can be converted to a Verilog-AMS model or a Labeled Hybrid Petri Net formal model. Results are presented for the model generation, simulation, and verification of a PLL phase detector circuit.
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