Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits
Jie Zhang
Patil, N.P.
Mitra, S.
Stanford Univ., Stanford, CA;
This paper appears in: Design, Automation and Test in Europe, 2008. DATE '08
Publication Date: 10-14 March 2008
On page(s): 1009-1014
Location: Munich,
ISBN: 978-3-9810801-3-1
INSPEC Accession Number: 10278090
Digital Object Identifier: 10.1109/DATE.2008.4484813
Current Version Published: 2008-04-11
Abstract
Metallic carbon nanotubes (CNTs) create source-drain shorts in carbon nanotube field effect transistors (CNFETs), causing excessive leakage, degraded noise margin and delay variation. There is no known CNT growth technique that guarantees 0% metallic CNTs. Therefore, metallic CNT removal techniques are necessary. Unfortunately, such removal techniques alone are imperfect and insufficient. This paper demonstrates the necessity for co-optimization of processing techniques for metallic CNT removal together with CNFET-based circuit design. We present a probabilistic CNFET circuit model which forms the basis for such co-optimization, and use the model to derive design and processing guidelines that enable design of CNFET-based digital circuits with practical constraints on leakage, noise margin and delay variations. These guidelines are essential for designing robust metallic- carbon-nanotube-tolerant digital circuits.
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