Differential Analog Layout for Improved ASET Tolerance
Kelly, A.T.
Fleming, P.R.
Holman, W.T.
Witulski, A.F.
Bhuva, B.L.
Massengill, L.W.
Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN;
This paper appears in: Nuclear Science, IEEE Transactions on
Publication Date: Dec. 2007
Volume: 54,
Issue: 6, Part 1
On page(s): 2053-2059
Location: Snowmass Village, CO, USA,
ISSN: 0018-9499
INSPEC Accession Number: 10062076
Digital Object Identifier: 10.1109/TNS.2007.910124
Current Version Published: 2007-12-12
Abstract
Single-event transients (SETs) affecting a single side of a differential data path have been shown to cause signal degradation and data loss. A radiation hardened by design (RHBD) transistor layout technique is demonstrated that promotes charge collection on both sides of the differential data path. The induced common-mode error voltage is suppressed by the differential circuit, significantly reducing the SET amplitude.
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