NXG05-3: Scalable Layer-2/Layer-3 Multistage Switching Architectures for Software Routers
Bianco, A.
Finochietto, J.M.
Galante, G.
Mellia, M.
Mazzucchi, D.
Neri, F.
Dipt. di Elettron., Politec. di Torino, Turin;
This paper appears in: Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE
Publication Date: Nov. 27 2006-Dec. 1 2006
On page(s): 1-5
Location: San Francisco, CA,
ISSN: 1930-529X
ISBN: 1-4244-0356-1
INSPEC Accession Number: 10284969
Digital Object Identifier: 10.1109/GLOCOM.2006.343
Current Version Published: 2007-04-16
Abstract
Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open-source software. When considering maximum performance in terms of throughput, PC-based routers suffer from limitations stemming from the single PC architecture, e.g., limited bus bandwidth, and high memory access latency. To overcome these limitations, in this paper we present a multistage architecture that combines a layer-2 load-balancer front-end and a layer-3 routing back-end, interconnected by standard Ethernet switches. Both the front-end and the back-end are implemented using standard PCs and open- source software. After describing the architecture, evaluation is performed on a lab test-bed, to show its scalability. While the proposed solution allows to increase performance of PC- based routers, it also allows to distribute packet manipulation functionalities, and to automatically recover from component failures.
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