Design and optimization of high voltage analog and digital circuitsbuilt in a standard 5 V CMOS technology
Ballan, H.
Declercq, M.
Krummenacher, F.
Electron. Lab., Swiss Federal Inst. of Technol., Lausanne;
This paper appears in: Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Publication Date: 1-4 May 1994
On page(s): 574-577
Meeting Date: 05/01/1994 - 05/04/1994
Location: San Diego, CA, USA
ISBN: 0-7803-1886-2
References Cited: 3
INSPEC Accession Number: 4916239
Digital Object Identifier: 10.1109/CICC.1994.379656
Current Version Published: 2002-08-06
Abstract
This paper presents a new family of high-voltage (HV) analog and
digital circuits which are fully compatible with a standard 5 V CMOS
technology, without any process change. On the basis of several
circuits, it is shown that HV design can be classified in three
categories, for which a common design methodology can be identified.
Detailed circuit sizing as well as measurements illustrate the
performance achieved with this technique
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
