The derivation and experimental verification of clocksynchronization theory
Palumbo, D.L.
NASA Langley Res. Center, Hampton, VA;
This paper appears in: Computers, IEEE Transactions on
Publication Date: Jun 1994
Volume: 43,
Issue: 6
On page(s): 676-686
ISSN: 0018-9340
References Cited: 17
CODEN: ITCOB4
INSPEC Accession Number: 4717605
Digital Object Identifier: 10.1109/12.286301
Current Version Published: 2002-08-06
Abstract
The objective of this work is to validate mathematically derived
clock synchronization theories and their associated algorithms through
experiment. Two theories are considered, the Interactive Convergence
Clock Synchronization Algorithm and the Mid-Point Algorithm. Special
clock circuitry was designed and built so that several operating
conditions and failure modes (including malicious failures) could be
tested. Both theories are shown to predict conservative upper bounds
(i.e., measured values of clock skew were always less than the theory
prediction). Insight gained during experimentation led to alternative
derivations of the theories. These new theories accurately predict the
clock system's behavior. It is found that a 100% penalty is paid to
tolerate worst case failures. It is also shown that under optimal
conditions (with minimum error and no failures) the clock skew can be as
much as 3 clock ticks. Clock skew grows to 6 clock ticks when failures
are present. Finally, it is concluded that one cannot rely solely on
test procedures or theoretical analysis to predict worst case conditions
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