Bandwidth Extension Techniques for CMOS Amplifiers
Shekhar, S.
Walling, J.S.
Allstot, D.J.
Dept. of Electr. Eng., Univ. of Washington, Seattle, WA;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2006
Volume: 41,
Issue: 11
On page(s): 2424-2439
Location: Lille, France,
ISSN: 0018-9200
INSPEC Accession Number: 9159462
Digital Object Identifier: 10.1109/JSSC.2006.883336
Current Version Published: 2006-10-30
Abstract
Inductive-peaking-based bandwidth extension techniques for CMOS amplifiers in wireless and wireline applications are presented. To overcome the conventional limits on bandwidth extension ratios, these techniques augment inductive peaking using capacitive splitting and magnetic coupling. It is shown that a critical design constraint for optimum bandwidth extension is the ratio of the drain capacitance of the driver transistor to the load capacitance. This, in turn, recommends the use of different techniques for different capacitance ratios. Prototype wideband amplifiers in 0.18-mum CMOS are presented that achieve a measured bandwidth extension ratio up to 4.1 and simultaneously maintain high gain (>12 dB) in a single stage. Even higher enhancement ratios are shown through the introduction of a modified series-peaking technique combined with staggering techniques. Ultra-wideband low-noise amplifiers in 0.18-mum CMOS are presented that exhibit bandwidth extension ratios up to 4.9
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