System-on-chip test scheduling with reconfigurable core wrappers
Larsson, E.
Fujiwara, H.
Dept. of Comput. Sci., Linkoping Univ., Sweden;
This paper appears in: Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publication Date: March 2006
Volume: 14,
Issue: 3
On page(s): 305- 309
ISSN: 1063-8210
INSPEC Accession Number: 8892489
Digital Object Identifier: 10.1109/TVLSI.2006.871757
Current Version Published: 2006-04-24
Abstract
The problem with increasing test application time for testing core-based system-on-chip (SOC) designs is addressed with test architecture design and test scheduling. The scan-chains at each core are configured into a set of wrapper-chains, which by a core wrapper are connected to the test access mechanism (TAM), and the tests are scheduled in such a way that the test time is minimized. In this paper, we make use of reconfigurable core wrappers that, in contrast to standard wrappers, can dynamically change (reconfigure) the number of wrapper-chains during test application. We show that by using reconfigurable wrappers the test scheduling problem is equivalent to independent job scheduling on identical machines, and we make use of an existing preemptive scheduling algorithm that produces an optimal solution in linear time (O(n); n is the number of tests). We also show that the problem can be solved without preemption, and we extend the algorithm to handle: 1) test conflicts due to interconnection tests and 2) cases when the test time of a core limits an optimal usage of the TAM. The overhead in logic is given by the number of configurations, and we show that the upper-bound is three configurations per core. We compare the proposed approach with the existing technique and show, in comparison, that our technique is 2% less from lower bound.
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