Finding optimal L1 cache configuration for embedded systems
Janapsatya, A.
Ignjatovic, A.
Parameswaran, S.
Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW;
This paper appears in: Design Automation, 2006. Asia and South Pacific Conference on
Publication Date: 24-27 Jan. 2006
On page(s): 6 pp.-
Location: Yokohama,
ISBN: 0-7803-9451-8
INSPEC Accession Number: 8912866
Digital Object Identifier: 10.1109/ASPDAC.2006.1594783
Current Version Published: 2006-03-13
Abstract
Modern embedded system execute a single application or a class of applications repeatedly. A new emerging methodology of designing embedded system utilizes configurable processors where the cache size, associativity, and line size can be chosen by the designer. In this paper, a method is given to rapidly find the L1 cache miss rate of an application. An energy model and an execution time model are developed to find the best cache configuration for the given embedded application. Using benchmarks from Mediabench, we find that our method is on average 45 times faster to explore the design space, compared to Dinero IV while still having 100% accuracy
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