Global routing techniques for an automatic mixed analog/digital IClayout compiler
Lin, Z.-M.
Dept. of Electr. Eng., Maryland Univ., College Park, MD;
This paper appears in: Southeastcon '91., IEEE Proceedings of
Publication Date: 7-10 Apr 1991
On page(s): 392-396 vol.1
Meeting Date: 04/07/1991 - 04/10/1991
Location: Williamsburg, VA, USA
ISBN: 0-7803-0033-5
References Cited: 27
INSPEC Accession Number: 4076512
Digital Object Identifier: 10.1109/SECON.1991.147780
Current Version Published: 2002-08-06
Abstract
Global routing techniques for an automated analog/digital IC
layout compiler are presented. The global router routes in a net-by-net,
high-sensitivity-net-first order. Minimum trees are searched for the
interconnection of sensitive nets and power nets. For the routing of
noise nets, the router provides a net-crossing-free terminal assignment
between sensitive nets and noise nets for the routing of channels.
Efficient terminal assignment and extraction techniques for the router
are also presented
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